1. Field of the Invention
The present invention generally relates to data transfer circuits, and particularly relates to a data transfer circuit which transfers data between areas having different clock frequencies.
2. Description of the Related Art
As the operation speed of LSI circuits increases, a gap in operation frequencies is widened between the interior of the LSI circuits and the exterior of the LSI circuits. This leads to a need for an operation sequence circuit that transfers data between areas having different operation frequencies. Also, where complex procedures having been implemented by software are now to be implemented through hardware, a plurality of LSI circuits having, different functions need to be connected together. This also leads to a need for an operation sequence circuit that transfers data between areas of different operation frequencies.
Attention is now directed to data transfer between an area having a faster clock rate and a plurality of areas having a slower clock rate. FIG. 1 and FIG. 2 are illustrative drawings showing operation sequence circuits that are situated between the area having a faster clock rate and the plurality of areas having a slower clock rate.
When data is transferred from the area of a faster clock rate to the areas of a slower clock rate (FIG. 1), flip-flops operating at the slower clock rate receive data, and, then, the data are transmitted to the areas of the slower clock rate by selecting a destination of transfer by use of a selector. When data is transferred from the areas of the slower clock rate to the area of the faster clock rate (FIG. 2), data sources operating at the slower clock rate are selected by a selector, and flip-flops operating at the faster clock rate receive data, followed by transmitting the data to the area of the faster clock rate.
FIG. 3 is a drawing showing interface signals used by an operation sequence circuit that transfers data between areas of different frequencies. In FIG. 3, data transfer is conducted between an area R1A operating at a clock cycle tCLK1 and two areas R2A and R2B operating at a clock cycle tCLK2. A signal input from the area R1A and a signal output to the area R1A are IN_1A and OUT_1A respectively. A signal input from the area R2A and a signal output to the area R2A are IN_2A and OUT_2A respectively. Further, a signal input from the area R2B and a signal output to the area R2B are IN_2B and OUT_2B, respectively.
tCLK1 is equal to or shorter than tCLK2. In the following, tCLK1:tCLK2 is assumed to be 1:2, for the sake of explanation.
FIG. 4 is a timing chart showing data transfer timings in the case of FIG. 1. This relates to a case in which data is transferred from an area of a faster clock area to an area of a slower clock area.
When data is transferred one by one from the area R1A operating at the clock cycle tCLK1 to the areas R2A and R2B operating at the clock cycle tCLK2, the area R1A supplies data1 at t1 and data2 at t3. The area R2A receives data1 at t4, and the area R2B receives data2 at t6. Since the data needs to be supplied at the rate corresponding to the slower frequency, data1 and data2 of IN_1A need to be spaced apart by one clock cycle.
FIG. 5 is a timing chart showing data transfer timings in the case of FIG. 2. This relates to a case in which data is transferred from an area of a slower clock area to an area of a faster clock area.
When data is transferred one by one from the areas R2A and R2B operating at the clock cycle tCLK2 to the area R1A operating at the clock cycle tCLK1, the area R2A supplies data1 at t1, and the area R2 B supplies data2 at t3. The area R1A receives data1 at t4, and receives data2 at t6. Since the data are received at the rate corresponding to the slower frequency, data1 and data2 of OUT_1A need to be spaced apart by one clock cycle.
Accordingly, there is a need for a scheme in which delays in data transfer is reduced when transferring data between areas of different operation frequencies.